1. Field of the Invention
The present invention relates to description style conversion method, program, and system of a logic circuit which enable a high-speed simulation of the logic circuit described by using a hardware description language, and particularly relates to description style conversion method, program, and system of a logic circuit which enable a high-speed simulation by converting a logic circuit described in a netlist style to an RTL style.
2. Description of the Related Arts
Conventionally, text-based designing operations using a hardware description language (HDL; Hardware Description Language) such as Verilog-HDL have been performed as a designing method which is an alternative to a circuit diagram for a large-scale logic circuit. The designing operations by means of the HDL are generally performed in the following procedures.    (1) An HDL file (function description file) is generated by describing functions of circuit modules in a hardware description language in a text editor.    (2) The operation thereof is checked by using an HDL simulator of the HDL file.    (3) A netlist is generated from the operation-checked HDL file by using a logic synthesis tool. In logic designing using such a conventional HDL, they are basically described in an RTL style which is known as an RTL (Register Transfer Level) description; however, a data-path-based circuit or a DFT (Design For Test) circuit which is required to be operated at a high speed in a GHz order is often described in a netlist style which is known as a gate level description. Herein, the RTL description referred to as an RTL style is a description of an HDL expressing logics to be realized by registers and the logic functions between the registers, and the description describes the state of the values of the registers which undergo transitions. The gate level description referred to as a netlist style is a level which describes them in a list expressing gates and cell-based (lower-level modules converted into components and registered in libraries as instances) connection relations in an ASIC, and is used for example when a high speed or a high density which cannot be realized by the RTL description is required. As described above, logic designing of LSI circuits is described in the RTL style and the netlist style by using HDL, and, in designing, whether the functions of the logic circuits of the HDL properly operate or not is examined by use of a logic simulator. Below Patent Documents 1 to 6 are provided as conventional techniques related to simulations of logic circuits described in HDLs.
JP06-348775 provides a system which speeds up a simulation of a transistor/gate level simulation by converting transistors into gates, separating them into combinational circuits and sequential circuits, and converting them into RTL. JP07-129632 provides a system which speeds up a simulation of a gate level simulation by subjecting sequential circuits to clock synchronization by utilizing clock signals, optimizing activation timing of the sequential circuits, and then performing conventional optimization processes. JP10-069505 provides a system which speeds up a simulation of logic circuits simulation by performing an operation of grouping them in event execution units. JP2006-004244 provides a system which speeds up a simulation of a gate level simulation by determining gates which can be eliminated and eliminating them. JP09-311822 provides a system which speeds up a simulation by converting RTL into a netlist, performing deletion of inactive parts of circuits and moving/integrating registers with respect to the netlist, and reconverting it into RTL. JP11-085832 provides a system which speeds up a simulation of an RTL simulation by integrating a condition execution unit and a data computing unit which is subsequent to that.
However, when the operation of a large-scale LSI circuit including many circuits described in the netlist style is to be examined by a logic simulator, there is a problem that examination of the part described in the netlist style takes a lot of time. Specifically, in the case of a general logic simulator, a simulation is performed in an event-driven method; however, in the case of the netlist style, the number of events is considerably increased, and the execution time of the simulator is considerably lengthened. In the event-driven method simulation herein, attention is focused on an element such as a logic gate having a signal change (event), merely the element in the next step of the event generated element is subjected to computing processing, change in the signal is successively transmitted to the next step when the output of the element is changed, and not only logical values but also delay between events can be calculated. The below described systems are provided as systems which solve the problem of the simulation execution time of the netlist style.
(1) Simulation According to Cycle-Based Method
In a simulation of a cycle-based method, delay time of elements is ignored, computing order is statically determined in preprocessing, and, upon execution, computation is performed merely once in each clock cycle. Although timing examination cannot be performed, compared with the event-driven method, the amount of computation is significantly reduced, and operation which is about several tens to a hundred times faster can be performed.
(2) Simulation Using Hardware Emulator
A simulation by means of a hardware emulator is a simulation in which a logic simulator of the event-driven method is made into dedicated hardware, is designed to enhance the parallel property of processing as much as possible, is several ten to several hundred times faster than the logic simulator of the event-driven method, has no restriction on the object circuit, and can perform timing examination. However, the simulation according to the cycle-based method is basically for a synchronous circuit, has restrictions on the description of HDL, and is not general. The hardware emulator is extremely expensive, and therefore the burden in terms of cost is large. Therefore, a system which executes a simulation of logic circuits described in the netlist style at low cost without restrictions of the description of HDL is desired.